What are the differences between Xilinx 7 series FPGA clocks and previous generations?

Differences in clocking resources between 7 series FPGAs and previous generation FPGAs

Overview of Clock Resource Connections

1. Overview of clock resource architecture

1.1 Overview of Clock Resources

A global clock tree allows synchronizing block clocks across the entire FPGA device.

The I/O clock and region clock trees allow up to three vertically adjacent clock regions to be clocked.

Each CMT contains a mixed-mode clock manager (MMCM) and a phase- locked loop (PLL), located in the CMT column next to the I/O column.

To provide clocking, each 7 series device is divided into clock regions.

The number of clock regions varies with device size, from one clock region in the smallest device to 24 clock regions in the largest device.

The clock region includes 50 CLBs and all synchronization blocks (eg: CLBs, I/Os, serial transceivers DSPs , block RAMs , CMTs) in a region of one I/O bank (50 I/Os), with the center There is a horizontal clock row (HROW).

Each clock region spans 25 CLBs up and down from HROW and horizontally across each side of the device.

1.2 Overview of Clock Routing Resources

Each I/O bank contains clock-enabled input pins that bring user clocks to 7 Series FPGA clock routing resources. Along with dedicated clock buffers , clock input pins introduce user clocks to:

Global clock lines for the same upper/lower half of the device

Clock lines of the same I/O Bank and vertically adjacent I/O Banks

Regional clock lines for the same clock region and vertically adjacent clock regions

CMTs within the same clock region and vertically adjacent clock regions with constraints

Each 7 series device has 32 global clock lines that can clock and provide control signals to all timing resources throughout the device. The global clock buffer (BUFGCTRL, shortened to BUFG in this user guide) drives the global clock line and is used to access the global clock line. Each clock region can use 12 horizontal clock lines in the clock region to support up to 12 global clock lines.

Global clock buffer:

Can be used as a clock enable circuit to enable or disable clocks spanning multiple clock regions

Available as a glitch-free multi- plexer :

Choose between two clock sources

Switching from a failed clock source

Typically driven by a CMT for:

Eliminate clock distribution delays

Adjust the clock delay relative to another clock

Horizontal clock buffers (BUFH/BUFHCE) allow access to global clock lines in a single clock region through horizontal clock lines. It also acts as a clock enable circuit (BUFHCE) to independently enable or disable clocks spanning a single clock region. Up to 12 clocks can be supported using 12 horizontal clock lines in each clock region. Every 7 series FPGA has regional clock trees and I/O clock trees that can clock all timing resources within a clock region. Each device also features a multi-clock region buffer (BUFMR) that allows region and I/O clocks to span up to three vertically adjacent clock regions.

The I/O clock buffer (BUFIO) drives the I/O clock tree, providing access to all sequential I/O resources in the same I/O bank.

A regional clock buffer (BUFR) drives a regional clock tree that drives all clock destinations in the same clock region, with programmable input clock frequency.

Immediately next to the programmable serializer/deserializer in the IOB (see the Advanced Select Logic Resources chapter in the UG471 7 Series FPGA SelectIO Resources User Guide), the BUFIO and BUFR clock buffers allow source-synchronous systems to span clock domains, while No additional logic resources are required.

When used with an associated BUFR or BUFIO, multiple clock region buffers (BUFMRs) can be used to drive adjacent clock regions and I/O clock trees.

Up to four unique I/O clocks and four unique regional clocks can be supported in a clock region or I/O bank.

High-performance clock routing connects certain outputs of the CMT to I/Os with very low jitter and minimal duty cycle distortion.

1.3 Overview of CMT

Each 7 series FPGA has up to 24 CMTs, and each CMT consists of an MMCM and a PLL. MMCMs and PLLs are used as frequency synthesizers for very wide frequency ranges, as jitter filters for external or internal clocks , and for low-skew clocks. The PLL contains a subset of MMCM functionality. The 7 Series FPGA clock input connections allow multiple sources to provide reference clocks to the MMCM and PLL.

7 Series FPGA MMCMs have infinite fine phase shift capability in any direction and can be used in dynamic phase shift mode. MMCMs also have a fractional counter in the feedback path or one of the output paths, enabling further refinement of frequency synthesis capabilities.

The LogiCORE IP Clocking Wizard can be used to help create clocking networks in 7 Series FPGA designs using MMCMs and PLLs. A graphical user interface is used to collect clock network parameters. The Timing Wizard selects the appropriate CMT resource and configures the CMT resource and associated clock routing resources in an optimal way.

1.1.3 Clock Buffering, Management and Routing

Figure 1 is a high-level view of the 7 Series FPGA clocking structure. The vertical clock centerline (â‘ clock backbone) divides the device into adjacent left and right regions, while the horizontal centerline (â‘¡) divides the device into top and bottom sides. Resources in the clock backbone are mirrored on both sides of the horizontally adjacent region, extending some of the clocking resources to the horizontally adjacent region. The top and bottom (â‘¢) separate two sets of global clock buffers (BUFGs) and impose some restrictions on how they can be connected. However, BUFGs do not belong to the clock region and can reach any clock point on the device. All horizontal clock resources are contained in the center of the clock region horizontal clock row (HROW) (â‘£), while vertical, non-regional clock resources are contained in the clock trunk or CMT trunk.

Figure 1. View of the high-level clocking structure of a 7 Series FPGA. Figure 2 is a high-level overview of the clocking resources available within a clocking region and their basic connections.

Figure 2. Basic view of the clock area In the figure, we can see:

The global clock buffer (â‘ ) can enter each region through HROW, even if it is not physically located in the region.

The horizontal clock buffer (â‘¡BUFH) drives each clock point in this region through HROW.

BUFGs and BUFHs share routing paths in HROW (â‘¢).

The I/O buffer (BUFIO) and the regional clock buffer (BUFR) are located inside the I/O bank (â‘£). BUFIO only drives I/O clock resources, while BUFR drives I/O resources and logic resources.

BUFMR supports multi-region linking of BUF IOs and BUFRs. The clock input (chip *CC pin ⑤) connects the external clock to the clock resource on the device. Certain resources can be connected to the top and bottom regions through the CMT backbone clock network (â‘¥).

Figure 3 shows a more detailed view of the clocks in a single clock region on the right edge of the device. In this figure, we can see the clock resources that can be driven after the external clock input pins SRCC and MRCC enter the I/O Bank, as well as the interconnection between CMT resources and the outside world.

Figure 3. Single clock region (right side of device)

Figure 4 shows more detailed global BUFG and regional BUFH/CMT/CC pin connections and the number of resources available within a region (right region shown here).

Figure 4. BUFG/BUFH/CMT clock region details In Figure 4, we can see:

Either of the SRCC and MRCC clock input pins can drive the PLL/MMCM in the CMT and BUFH.

BUFGs appear to be located in this area, but can actually be located elsewhere in the clock backbone.

BUFG and BUFH share 12 routes in HROW that can drive all clock points within the region. BUFGs can also drive BUFHs (not shown in Figure 4), allowing individually enabled clocks (CEs) on other global clock distributions.

A GT Quad has ten dedicated channels to drive the CMT and clock buffers.

BUFRs located in an I/O bank have four traces driving logic, CMT, and clock points in BUFG. CMTs can use the CMT backbone to drive other CMTs in adjacent areas, but with limitations. Similarly, a clock input pin can drive a CMT in an adjacent region with the same constraints.

The clock input pins can drive the BUFG anywhere on the same top/bottom of the device. There are four traces in the CMT backbone to support connections between vertical areas.

The logic interconnect drives the CE pins of BUFG and BUFH. The logic interconnect can also drive the clock to the same buffer, but care must be taken as timing is unpredictable. Figure 5 shows the BUFR/BUFMR/BUFIO clock region details.

Figure 5, BUFR/BUFMR/BUFIO clock region details In Figure 5, we can learn:

Each I/O bank contains four BUFIOs and four BUFRs. Each of these clock buffers can be driven by a dedicated input clock pin pair (_CC pin), or can be driven directly by a specific output clock of the MMCM.

Two clock-enabled input pin pairs, called MRCCs, support multi-region clocking schemes. An MRCC pin pair can drive a specific BUFMR, which in turn can drive BUFIOs and BUFRs in the same and adjacent regions, facilitating multi-region/bank interfaces

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